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The next, we move to pipelining,

so pipeline technique.

So here you can see we have a reference circuit like this.

We have two registers here and one register here.

So this is the datapath to calculate log(|a+b|).

And you can see the min clock period of

this circuit equals clock-to-Q of this transistor plus

the delay of the logic plus

the setup time of this register. Right?

If, so, if we want to decrease the clock period,

in other words increase the frequency of the circuit,

we, at first we'll decrease the delay of the logic.

Because normally,

tp,logic determines the performance of the circuit.

It accounts for the big portion of clock period.

So one approach is to,

we can insert some registers into the logics,

for example, this is the adder，

this is the absolute operation,

this is the log operation.

We can insert two registers.

In this case you can find out the min clock

period is reduced to clock-to-Q plus

the maximum value of the adder,

the absolute and the logarithm,

OK? Plus setup time.

So therefore the clock period is substantially reduced.

The example of pipelined computation.

You can find out that,in the adder,

in the first clock period, the adder is performing a1+b1.

Then in the clock period two,

then the absolute value is performing the calculation of |a1+b1|.

Then in the clock period three,

the logarithm is performing the logarithm operation. Right?

So all the stages are fully occupied,

therefore we can pipeline, we can process the input values.

So in classic (not at the edge of technology)

logic delay is larger than register delay overhead.

So register delay overhead includes

the propagation delay plus setup delay.

Then setup requirement.

In cascade of logic operators,

each operator is “usefully active” during a part of the cycle.

The advantage of pipelining is that it increases throughput

in the sense that the critical path becomes shorter. Right?

We can see here the critical path of this one is equal to this one.

However the critical path of this one equals t clock-to-Q plus

the maximum value of this one adder,

absolute operation and logarithm operation.

So also the pipelining increases the efficient usage of the logic.

So if all the stages are fully occupied.

The bad thing is that the pipelining increases

the latency in number of the clock cycles.

It can be a problem, right?

Latency means so after 3 clock cycles,

we can obtain the output of the first input.

So that's an issue.

So latency of the cycle numbers is increased.

And this is, here I'd like to show you the latch based pipelines.

So this is a latch, this is another latch.

So when clock equals 0, which means this is off.

OK? This is on

then it's time to compute the F.

When clock bar equals 0,

this is off,

then that's the time to compute the G. OK?

So race condition when clk-clk bar overlap.

We still have race condition here.

So here, if we have race condition,

we can use C2MOS pipeline technology,

because C2MOS pipeline is race free as long as the logic

functions between the latches are non-inverting. OK?

Why is that?

You can see if it is inverting,it is a,

we have an inverter here.

Therefore you can find out that this one will pull it up,

then pull it down, and then pull it up.

So that's the issue.

So 0-0 overlap, this is 0-0 overlap.

This is off, this if off.

In 1-1 overlap, we have a similar situation.