当前课程知识点：数字集成电路分析与设计 > Sequential Logic Circuits II > 7.Schmitt Trigger > Video
So next, we are going to move to the
next content of this lecture,
the Schmitt trigger.
So Schmitt trigger. This is a symbol
of non-inverting Schmitt trigger.
And here you can find out in Schmitt trigger,
we have two switching thresholds.
When the input goes from low to high,
OK? We have one switching threshold which is defined as VM+.
When the input goes from high to low,
then we have another switching threshold defined as VM-.
So this is the definition in
this course to make things clear.
So we have two important properties of Schmitt trigger.
It responds to a slowly changing input waveform
with a fast transition time at the output.
What does it mean?
You can find out, if this is the input,
because we have VM- here and VM+ here,
If the input makes very fast variation,
then the output is something like this. OK?
So that's why it responds to a slowly
changing input waveform with a fast transition time.
Because this is VM+, this is VM-,
if the voltage is bigger than VM-,
then the state of the Schmitt trigger will not change. OK?
So turning a noisy or slowly varying input
signal into a clean digital output signal.
And the voltage-transfer characteristic of the device
displays different switching thresholds
for positive- and negative-going input signal.
I can show you an example.
So here we have two inverters and one more inverter here.
When the input makes, goes from 0 to 1，
for example, so if this is 0,
then this is 1,
this is 1,this is off, right?
This is 1, when this is 1, then this is 0.
If this is 0, then M4 is turned on. Right?
So because this is 0, then M3 is turned off.
So in the pull-up network
we have two PMOS transistors in parallel.
However in pull-down network
we only have one NMOS transistor. OK?
Then this is Vin, goes from 0 to 1.
If Vin goes from 1 to 0, OK? If this is 1,
then this one equals 0,X equals 0.
If X equals 0, then the Vout equals 1.
If Vout equals 1, then M4 is turned off, then M3 is turned on. OK?
So when if Vin goes from 1 to 0,
then we have two NMOS transistors
in parallel in the pull-down network,
and we only have one transistor,
PMOS transistor in the pull-up network.
So this one can exhibit a different VM+ and VM-, like this.
The switching threshold of the CMOS inverter
can be shifted by modifying this one and this one,
the ratio of this one over this one. OK?
And for example, if we assume that the size of transistor1
equals this one, transistor2 equals this one, OK?
And transistor3 equals this one, transistor4 equals this one,
so you can find out when input makes,
goes from low to high，we have VM+ here.
when input goes from high to low，
we have VM- here. OK?
And if we increase the parameter k,
we can shift the VM+. OK?
And another alternative CMOS Schmitt trigger is illustrated here,
you can see we have two PMOS transistors in series
and one PMOS transistor located here,
and we have two NMOS transistors in series
and one NMOS transistor located here.
So why this is a Schmitt trigger?
I can analyze the function of this one.
When the input goes from 0 to 1 first,
then you can analyze when input goes from 1 to 0 yourself. OK?
So here you can find out,
if the input is equal to 0 initially, OK?
If this one is equal to 0,
then the voltage here is high，voltage here Vout is high. OK?
If Vout is high, then transistor M5 is turned on. Right?
And, and because the input of this one
and this one are both equal to 0,
so this one is off, this one is off.
So if we increase the voltage potential of the Vin,
then the transistor M1 may be turned on if the Vgs of
transistor M1 is bigger than the threshold voltage of M1. OK?
If we increase the voltage of Vin further,
at some situation, you can find out when the Vx reaches,
so when the difference between this one and this one
is bigger than the threshold voltage of transistor M2
then transistor M2 is turned on. Right?
If transistor M2 is turned on,
then the Vout will be discharged through transistor M2 and M1. OK?
So here we go one more time.
If we increase this one,
increase this one from 0,then M1 is turned on,
then the voltage potential here,
we increase this one, then this one is decreased.
The voltage potential of this one minus by this one,
sometime the threshold voltage,is bigger than threshold voltage of M2,
then M2 is turned on,
then the Vout is discharged through M2.
So in this case
we can calculate the VM+ and VM- quantitatively. OK?
Here we can assume that approximately,
VM is chosen to be the input value at the exact time when the “Out”
starts to decrease (VM+) or increase (VM-). OK?
So that's another alternative CMOS Schmitt trigger.
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--文档
-1.Introduction to Digital IC
--Video
-2.Architecture of Digital Processor
--Video
-3.Full Custom Design Methodology
--Video
-4.Semicustom Design Methodology
--Video
-5.Quality Metric of Digital IC
--Video
-6.Summary and Textbook Reference
--Video
-7.HW--作业
-7.PPT
--补充材料1
--补充材料2
-Key Points Review of Last Lecture
--Video
-1.Introduction
--Video
-2.The Diode
--Video
-3.The MOSFET Transistor
--Video
-4.Secondary Effects
--Video
-5.Summary and Textbook Reference
--Video
-6.HW--作业
-6.PPT
--补充材料
-Key Points Review of Last Lecture
--Video
-1.Introduction
--Video
-2.Static Behavior
--Video
-3.HW--作业
-3.PPT
--补充材料
-Key Points Review of Last Lecture
--Video
-1.Dynamic Behavior I
--Video
-2.Dynamic Behavior II
--Video
-3.Power Dissipation
--Video
-4. Summary and Textbook Reference
--Video
-5.HW--作业
-5.PPT
--补充材料
-1.Introduction
--Video
-2.Static CMOS Design I
--Video
-3.Static CMOS Design II
--Video
-4.HW--作业
-4.PPT
--补充材料
-Key Points Review of Last Lecture
--Video
-1.Static CMOS Design III
--Video
-2.Static CMOS Design IV
--Video
-3.Dynamic CMOS Design
--Video
-4.Summary
--Video
-5.HW--作业
-5.PPT
--补充材料
-1.Introduction I
--Video
-2.Introduction II
--Video
-3. Static Latches and Registers I
--Video
-4.Static Latches and Registers II
--Video
-5.Static Latches and Registers III
--Video
-6.HW--作业
-6.PPT
--补充材料
-1.Key Points Review
--Video
-2.Dynamic Latches and Registers I
--Video
-3.Dynamic Latches and Registers II
--Video
-4.Dynamic Latches and Registers III
--Video
-5.Pulse Register
--Video
-6.Pipelining
--Video
-7.Schmitt Trigger
--Video
-8.Summary and Textbook Reference
--Video
-9.HW--作业
-9.PPT
--补充材料
-1. Introduction
--Video
-2. Adder: Full Adder (Definition)
--Video
-3. Adder: Circuit Design
--Video
-4. Adder: Logic Design I
--Video
-5. Adder: Logic Design II
--Video
-6. Adder: Summary
--Video
-7.HW--作业
-7.PPT
--补充材料
-1. Key Points Review
--Video
-2. Multiplier
--Video
-3. Shifter
--Video
-4. Summary and Textbook Reference
--Video
-5. HW--作业
-5. PPT
--补充材料
-1. Introduction
--Video
-2. Capacitance
--Video
-3. Resistance
--Video
-4. Electrical Wire Models
--Video
-5. Summary and Textbook Reference
--Video
-6. HW--作业
-6. PPT
--补充材料
-1. Introduction
--Video
-2. Capacitive Parasitics
--Video
-3. Capacitive Parasitics II
--Video
-4. Resistive Parasitics
--Video
-5. Summary and Textbook Reference
--Video
-6. HW--作业
-6. PPT
--补充材料
-1. Assignment Solving
--Video
-2. The teaching assistants want to say
--Video
-1. Problem 1
--Video
-2. Problem 2
--Video
-3. Problem 3
--Video
-4. Problem 4
--Video
-5. Problem 5
--Video
-6. Problem 6
--Video
-7. Problem 7
--Video
-1. Problem 8
--Video
-2. Problem 9
--Video
-3. Problem 10
--Video
-4. Problem 11
--Video
-5. Problem 12
--Video
-6. Problem 13
--Video
-7. Problem 14
--Video
