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So still remember this picture?

At that time I introduced the major components

of the capacitance of the inverters.

So we know that this is capacitance

between the gate and drain

And we should think about the overlap

capacitance between the gate and drain,

as well as channel capacitance

So in terms of overlap capacitance

the Miller effect should be taken into account.

In terms of channel capacitance,

if we assume that the input is a step input.

Therefore we don’t have any channel

capacitance between the gate and drain

And these two are the junction capacitance,

which consists of three sidewalls

and one bottom plate junction capacitance

And this is the gate capacitance of the load gate, right?

Including the overlap capacitance

and channel capacitance. Right?

So at that time we ignore the capacitance

Contributed by the wire,

actually we have the capacitance like

this which is connected between VOUT and GND right?

So we, in reality we should

Lump all of them together into one capacitor,

located between the VOUT and GND

So in this lecture I would like to introduce

how we could calculate the capacitance of the wire

So this is the wire and this is the length of the wire.

This is the width of the wire

and this is the thickness of the wire. OK?

And we know that this one serves as

The plate which is placed above another plate

this one substrate right?

And between this plate,

I mean substrate and wire we have dielectric

SiO2 right? this is electric field,

this is electric field.

So the thickness of dielectric equals tox

So according to this we know

how to calculate the parallel-plate capacitance right?

Here we can make assumption

that the width of the wire is much bigger

much greater than the thickness of the dielectric.

So if we exploit the parallel-plate capacitance model.

The wire capacitance can be expressed as the capacitance equals

εox over tox times W times L. Right?

So this one stands for the area

Overlap area between the up plate and the bottom plate right?

And this is the permittivity of the dielectric

layer and tox is thickness of dielectric layer

And if the width and thickness are scaled by the factor of S. OK?

And also the length of the wire is scaled by a factor of SL.

therefore we can calculate that the scaling factor of the wire,

of the capacitance of the wire should be SL, right?

According to this

So this is very simple

This is the permittivity of the dielectric.

So the definition is that εox equals εr times ε0

ε0 here stands for the permittivity of the free space

Which is normalized to one. OK?

And εr here stands for the relative permittivity of the material. OK?

So this table gives us the permittivity,

relative permittivity of the different material.

So this is 1 for free space

Aerogel, this one, 1.5

And polyimides 3-4. And silicon dioxide equals 3.9. OK?

And aluminum and silicon

And in this foil you can find out

This is a cross-section view of the 0.25um interconnect

So you can see that with device dimensions scaling down

If you want to minimize the resistance of wires

it is desirable to keep the cross-section of the wires

As large as possible. Right?

Because the resistance is inversely proposal

to the area, the cross area of the wire. Right?

And also the, because the small value of W leads

to denser wiring and less area overhead.

Therefore we can witness a steady reduction in the W/H ratio.

Because this one, the W decreases, however,

W decreases to integrate more transistors

and length and wire on to the chip.

However at the same time

The thickness of the wire remain the same. Right?

Almost remain the same

to reduce the resistance.

Therefore we can witness a steady reduction

in the W/H ratio even below one.

If we have, you can find out if

we decrease the width and at the same time this one,

the thickness of the wire remain the same

therefore the fringing capacitance,

fringing capacitance I mean the capacitance

between this one, this one and this one

Become an issue, becomes an issue.This is fringing capacitance.

And also this one and this one. Right?

Here you can see we have wire and even the

Thickness of the wire is even bigger than the width of the wire.

So you can see this one. This is the thinner one.

And this is, the height is bigger

And this is smaller. Ok?

OK so in terms of the fringing capacitance,

so we have to consider the influence of the fringing capacitance

So how cloud we calculate the capacitance of the wire

So it is not simply using the parallel-plate capacitance

So we should decompose that one into two different capacitances.

One is the traditional parallel-plate capacitance.

The other one is, fringing, fringing capacitance

So here I can give you an example this is the wire

So we decompose this one into two kinds of capacitances.

One is the traditional parallel-plate capacitance

with the width of the wire equals W minus the thickness over two

W minus H over two. And the other component,

the other capacitance is the one to represent the fringing capacitance with.

It is modeled by the cylinder with diameter equals the thickness of the wire.

So this is the diameter equals H. OK?

So these two, these two could be expressed as this one

So cwire equals cpp plus cfringe

equals this one and this one. OK?

And here, I give you a picture to demonstrate the relationship

between the parallel-plate capacitance and fringing capacitance.

So in this picture you can see.

The x axis stands for the width over the thickness of the dielectric

So this is the thickness, this is the width.

And y axis stands for the capacitance. So this one

This one the dashed line here stands for the parallel-plate capacitance

and this one, the curve, this one,

the solid curve and the dashed curve stands for the total capacitance

So you can see that, when the W over tdi is bigger than 1.5 OK?

and in this area, in this area, the parallel-plate capacitance dominates.

However when this one, when W over tdi is less 1.5

In this area you can find out the fringing capacitance dominates. Right?

Because the total capacitance consists

of fringing capacitance and parallel capacitance

And one interesting thing is that

you can see when the W over tdi is less than 1

Then the total capacitance approaches 1pf/cm.

Therefore it doesn't have any relation with the width of the wire

So it is very interesting to say that

We know that this expression to calculate the capacitance

of the wire is relatively complex

So the most frequently used approach is to

Most foundry will give you a table

Therefore you can look into the table

to find out the capacitance between different layers

For example, this is the aluminum one and this is poly.

So the aluminum one, between the aluminum one and the poly.

The parallel-plate capacitance equals this one

And this one stands for the fringing capacitance

So for example this is upper layer and this is lower layer

and the shadow-less this one stands for the parallel-plate capacitance.

The unit is af/um2. And this one

The shadowed layer stands for fringing capacitance.

The unit is af/um

when calculate the interwire capacitance,

I mean calculate the fringing capacitance,

we have to take into account the fringing capacitance of the two sides, two sides.

Because every wire has two sides, have two sides.

So that is very important

I will give you an example,

if we have aluminum wire with length equals 10cm

and width equals 1um

so calculate the total capacitance

So here the parallel-plate capacitance equals this one. Right?

And this one is, this is the length of the wire times the width of the wire.

This is the area of the wire times this one

So this one the 30af/um2 comes from this one right? comes from this one

And also the fringing capacitance,

this is the length of the wire times the 40af/um2.

The 40af/um2 comes from this one, comes from this one. OK?

And also I mentioned that the number 2 should be taken into account.

Because of two sides. Every wire has two sides

Therefore total capacitance equals 11 pf, right?

This is Cgroud.

We name it as the capacitance between the wire and GND

And also besides the parallel-plate capacitance,

fringing capacitance,

we also have the capacitance between different wires.

That is called interwire capacitance

For example this,

the capacitance between this one and this one.

We have this one, right?

The interwire capacitance, also this one, also this one. OK?

And also we still have a table

Therefore we can look into the table to find out

The value of the interwire capacitance between different layers

For example, this one and this one and this one,

this is the biggest one, and this is the smallest one. OK?

So that capacitance between the aluminum 5 is

115 af/um. And between the poly is 40 af/um.

And also we have the capacitance,

interwire capacitance between

The aluminum 1, aluminum 2, aluminum 3, aluminum 4

And this picture tells us the relationship

between the total capacitance

and the ground capacitance and interwire capacitance.

Here you can see, this is the total capacitance

Which is the average value of the

interwire capacitance and the ground capacitance

And the ground capacitance consists of, just as I mentioned,

the parallel-plate capacitance

and fringing capacitance. Right?

So when x axis stands for W over H ratio.

So when this one W over H ratio less than 1.75

You can see the ground capacitance

is less than the interwire capacitance.

When this one is bigger,

then ground capacitance dominates

So that is why we have total capacitance like this

Here we know how to calculate the ground capacitance

and here if we suppose

that the second wire is routed alongside the first one

Separated by only the minimum allowed distance

to calculated the interwire capacitance,

therefore we can use this one to calculate,

to multiply by 95 af/um equal this one

So this one 95 af/um comes from this one aluminum 1 right?

And you can see the adjacent or the interwire capacitance

is almost the same as the ground capacitance

This is a multi-layer capacitance model.

And if we have layers like this.

For example this is layer n+1.

This is layer n. this is layer n-1

Therefore we have ground capacitance including the bottom

and top ground capacitance

as well as two adjacent or two interwire capacitances

This one and this one.

So the total capacitance equals Cbot plus Ctop plus two times Cadj

数字集成电路分析与设计课程列表:

Hspice

-1

--文档

Introduction and Implementation Strategies for Digital IC

-1.Introduction to Digital IC

--Video

-2.Architecture of Digital Processor

--Video

-3.Full Custom Design Methodology

--Video

-4.Semicustom Design Methodology

--Video

-5.Quality Metric of Digital IC

--Video

-6.Summary and Textbook Reference

--Video

-7.HW--作业

-7.PPT

--补充材料1

--补充材料2

The Devices

-Key Points Review of Last Lecture

--Video

-1.Introduction

--Video

-2.The Diode

--Video

-3.The MOSFET Transistor

--Video

-4.Secondary Effects

--Video

-5.Summary and Textbook Reference

--Video

-6.HW--作业

-6.PPT

--补充材料

The CMOS Inverter I

-Key Points Review of Last Lecture

--Video

-1.Introduction

--Video

-2.Static Behavior

--Video

-3.HW--作业

-3.PPT

--补充材料

The CMOS Inverter II

-Key Points Review of Last Lecture

--Video

-1.Dynamic Behavior I

--Video

-2.Dynamic Behavior II

--Video

-3.Power Dissipation

--Video

-4. Summary and Textbook Reference

--Video

-5.HW--作业

-5.PPT

--补充材料

Combinational Logic Circuits I

-1.Introduction

--Video

-2.Static CMOS Design I

--Video

-3.Static CMOS Design II

--Video

-4.HW--作业

-4.PPT

--补充材料

Combinational Logic Circuits II

-Key Points Review of Last Lecture

--Video

-1.Static CMOS Design III

--Video

-2.Static CMOS Design IV

--Video

-3.Dynamic CMOS Design

--Video

-4.Summary

--Video

-5.HW--作业

-5.PPT

--补充材料

Sequential Logic Circuits I

-1.Introduction I

--Video

-2.Introduction II

--Video

-3. Static Latches and Registers I

--Video

-4.Static Latches and Registers II

--Video

-5.Static Latches and Registers III

--Video

-6.HW--作业

-6.PPT

--补充材料

Sequential Logic Circuits II

-1.Key Points Review

--Video

-2.Dynamic Latches and Registers I

--Video

-3.Dynamic Latches and Registers II

--Video

-4.Dynamic Latches and Registers III

--Video

-5.Pulse Register

--Video

-6.Pipelining

--Video

-7.Schmitt Trigger

--Video

-8.Summary and Textbook Reference

--Video

-9.HW--作业

-9.PPT

--补充材料

Designing Arithmetic Building Blocks I

-1. Introduction

--Video

-2. Adder: Full Adder (Definition)

--Video

-3. Adder: Circuit Design

--Video

-4. Adder: Logic Design I

--Video

-5. Adder: Logic Design II

--Video

-6. Adder: Summary

--Video

-7.HW--作业

-7.PPT

--补充材料

Designing Arithmetic Building Blocks II

-1. Key Points Review

--Video

-2. Multiplier

--Video

-3. Shifter

--Video

-4. Summary and Textbook Reference

--Video

-5. HW--作业

-5. PPT

--补充材料

The Wire

-1. Introduction

--Video

-2. Capacitance

--Video

-3. Resistance

--Video

-4. Electrical Wire Models

--Video

-5. Summary and Textbook Reference

--Video

-6. HW--作业

-6. PPT

--补充材料

Coping with Interconnect

-1. Introduction

--Video

-2. Capacitive Parasitics

--Video

-3. Capacitive Parasitics II

--Video

-4. Resistive Parasitics

--Video

-5. Summary and Textbook Reference

--Video

-6. HW--作业

-6. PPT

--补充材料

Assignment Solving

-1. Assignment Solving

--Video

-2. The teaching assistants want to say

--Video

Exercise I

-1. Problem 1

--Video

-2. Problem 2

--Video

-3. Problem 3

--Video

-4. Problem 4

--Video

-5. Problem 5

--Video

-6. Problem 6

--Video

-7. Problem 7

--Video

Exercise II

-1. Problem 8

--Video

-2. Problem 9

--Video

-3. Problem 10

--Video

-4. Problem 11

--Video

-5. Problem 12

--Video

-6. Problem 13

--Video

-7. Problem 14

--Video

Video笔记与讨论

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