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Next we move to dynamic latches and registers

So here we have the comparison

between the static latch and dynamic latch.

You can see this is static latch.

So D is copied to Q,

when this is on, this is off

When this is off, then Q is preserved in

this cross coupled inverter pair though the TG gate

This is static latch. And this is the dynamic latch.

Here in the parentheses,

we say this is charge based

So the D is copied to Q bar.

Then here is charge based

So this is simpler than the static counterpart

And storage based on “capacitor” here,

and this one needs to be refreshed

because of the leakage through the TG gate as

well as leakage, some leakage though the gate

And floating node is very sensitive to noise and disturbance.

For example in some case when TG gate is turned off,

then this node is floating.

It is connected neither to power supply nor GND.

so this is floating node

And some low-power design techniques are

hard to be adopted because of the leakage currents.

For example, the clock cannot be too slow or halted right?

Otherwise, because we need to refresh the capacitor here,

so the clock cannot be too slow or halted

So we can see that the dynamic,

the circuit design technology is very hard to be applied

to some low performance applications

such as electronic watch. OK?

And also reading the value of the stored signal

from a capacitor without disrupting the charge requires

the availability of a device with a high-input impedance

What does that mean? That means the input resistance

of this one should be as large as possible

Therefore the charge could not be stored here. OK?

Making the dynamic latch pseudostatic

So we know if the node floating is not that good,

so we can add a weak feedback inverter.

Therefore it can improve the noise immunity

at a slight cost in delay.

Registers should always be made pseudostatic

or static unless they are used in a high-performance datapath

So here, actually I have shown you this before.

You can see we have a large inverter to drive the node.

This is called "Goliath" very hefty giant. OK?

And this is called, the small cute boy here,

small inverter here is called "David"

This one is used to hold the level via positive feedback

and must be overpowered by the input signal.

So this one should be weaker than the input signal,

should be overpowered by this one

And I'll introduce the dynamic transmission-gate

edge-triggered registers and clocked CMOS

and true single-phase clocked register one by one

The first: the dynamic transmission-gate edge-triggered register.

So it looks very simple compared

with that of the static implementation, right?

And here we have only one transmission gate.

This one transmission gate, another one,

another transmission gate and only two inverters here

And the setup time of this one should be equal

to the time it takes for the D to travel

through the T1 and arrive at the I1

So setup time equals the delay of the transmission gate

And propagation delay equals the time it takes

to travel through I1 and T2 and I3 until the Q is arrived

Then tclk-q equals this one, the delay of this one,

the delay of this one and the delay of this one

Then hold time. Because we don't have any clock overlap,

so hold time is equal to zero. OK?

So if we do have clock overlap that will give us the rise to

condition, race conditions

I will, we will discuss that later.

This foil tells us the impact of the non-overlapping clocks

So you can see we have CLK and CLK bar.

We have overlap between CLK and CLK bar.

So this is 0-0 overlap. This is 1-1 overlap. OK?

So during the 1-1 overlap,

you can see this transmission gate is turned on. Right?

And after the overlap,

this one is still turned on and this is off. OK?

So during the overlap the input data must remain stable

Otherwise for example if the input data is changing

then copied to the node A

Therefore node A will influence

the output after the 1-1 overlap.

So the D must be stable during the 1-1 overlap

In other word, the hold time of the register

should be greater than the time of 1-1 overlap

OK? This is 1-1 overlap. The other one is 0-0 overlap.

So in 0-0 overlap we can find out things here.

So here we have to make sure that the new “D” sampled

by the master stage does not propagate to the slave stage

This is the master stage. Right?

So the D could not transmit through the T1

And I1 then through T2 to point C. It is not allowed.

So the new data, the new "D" sampled

by the master stage does not propagate to the

slave stage during 0-0 overlap period

In other words, t overlap 0-0 is less

than the delay of T1, I1 as well as T2