当前课程知识点：数字集成电路分析与设计 > Sequential Logic Circuits II > 2.Dynamic Latches and Registers I > Video
Next we move to dynamic latches and registers
So here we have the comparison
between the static latch and dynamic latch.
You can see this is static latch.
So D is copied to Q,
when this is on, this is off
When this is off, then Q is preserved in
this cross coupled inverter pair though the TG gate
This is static latch. And this is the dynamic latch.
Here in the parentheses,
we say this is charge based
So the D is copied to Q bar.
Then here is charge based
So this is simpler than the static counterpart
And storage based on “capacitor” here,
and this one needs to be refreshed
because of the leakage through the TG gate as
well as leakage, some leakage though the gate
And floating node is very sensitive to noise and disturbance.
For example in some case when TG gate is turned off,
then this node is floating.
It is connected neither to power supply nor GND.
so this is floating node
And some low-power design techniques are
hard to be adopted because of the leakage currents.
For example, the clock cannot be too slow or halted right?
Otherwise, because we need to refresh the capacitor here,
so the clock cannot be too slow or halted
So we can see that the dynamic,
the circuit design technology is very hard to be applied
to some low performance applications
such as electronic watch. OK?
And also reading the value of the stored signal
from a capacitor without disrupting the charge requires
the availability of a device with a high-input impedance
What does that mean? That means the input resistance
of this one should be as large as possible
Therefore the charge could not be stored here. OK?
Making the dynamic latch pseudostatic
So we know if the node floating is not that good,
so we can add a weak feedback inverter.
Therefore it can improve the noise immunity
at a slight cost in delay.
Registers should always be made pseudostatic
or static unless they are used in a high-performance datapath
So here, actually I have shown you this before.
You can see we have a large inverter to drive the node.
This is called "Goliath" very hefty giant. OK?
And this is called, the small cute boy here,
small inverter here is called "David"
This one is used to hold the level via positive feedback
and must be overpowered by the input signal.
So this one should be weaker than the input signal,
should be overpowered by this one
And I'll introduce the dynamic transmission-gate
edge-triggered registers and clocked CMOS
and true single-phase clocked register one by one
The first: the dynamic transmission-gate edge-triggered register.
So it looks very simple compared
with that of the static implementation, right?
And here we have only one transmission gate.
This one transmission gate, another one,
another transmission gate and only two inverters here
And the setup time of this one should be equal
to the time it takes for the D to travel
through the T1 and arrive at the I1
So setup time equals the delay of the transmission gate
And propagation delay equals the time it takes
to travel through I1 and T2 and I3 until the Q is arrived
Then tclk-q equals this one, the delay of this one,
the delay of this one and the delay of this one
Then hold time. Because we don't have any clock overlap,
so hold time is equal to zero. OK?
So if we do have clock overlap that will give us the rise to
condition, race conditions
I will, we will discuss that later.
This foil tells us the impact of the non-overlapping clocks
So you can see we have CLK and CLK bar.
We have overlap between CLK and CLK bar.
So this is 0-0 overlap. This is 1-1 overlap. OK?
So during the 1-1 overlap,
you can see this transmission gate is turned on. Right?
And after the overlap,
this one is still turned on and this is off. OK?
So during the overlap the input data must remain stable
Otherwise for example if the input data is changing
then copied to the node A
Therefore node A will influence
the output after the 1-1 overlap.
So the D must be stable during the 1-1 overlap
In other word, the hold time of the register
should be greater than the time of 1-1 overlap
OK? This is 1-1 overlap. The other one is 0-0 overlap.
So in 0-0 overlap we can find out things here.
So here we have to make sure that the new “D” sampled
by the master stage does not propagate to the slave stage
This is the master stage. Right?
So the D could not transmit through the T1
And I1 then through T2 to point C. It is not allowed.
So the new data, the new "D" sampled
by the master stage does not propagate to the
slave stage during 0-0 overlap period
In other words, t overlap 0-0 is less
than the delay of T1, I1 as well as T2
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--文档
-1.Introduction to Digital IC
--Video
-2.Architecture of Digital Processor
--Video
-3.Full Custom Design Methodology
--Video
-4.Semicustom Design Methodology
--Video
-5.Quality Metric of Digital IC
--Video
-6.Summary and Textbook Reference
--Video
-7.HW--作业
-7.PPT
--补充材料1
--补充材料2
-Key Points Review of Last Lecture
--Video
-1.Introduction
--Video
-2.The Diode
--Video
-3.The MOSFET Transistor
--Video
-4.Secondary Effects
--Video
-5.Summary and Textbook Reference
--Video
-6.HW--作业
-6.PPT
--补充材料
-Key Points Review of Last Lecture
--Video
-1.Introduction
--Video
-2.Static Behavior
--Video
-3.HW--作业
-3.PPT
--补充材料
-Key Points Review of Last Lecture
--Video
-1.Dynamic Behavior I
--Video
-2.Dynamic Behavior II
--Video
-3.Power Dissipation
--Video
-4. Summary and Textbook Reference
--Video
-5.HW--作业
-5.PPT
--补充材料
-1.Introduction
--Video
-2.Static CMOS Design I
--Video
-3.Static CMOS Design II
--Video
-4.HW--作业
-4.PPT
--补充材料
-Key Points Review of Last Lecture
--Video
-1.Static CMOS Design III
--Video
-2.Static CMOS Design IV
--Video
-3.Dynamic CMOS Design
--Video
-4.Summary
--Video
-5.HW--作业
-5.PPT
--补充材料
-1.Introduction I
--Video
-2.Introduction II
--Video
-3. Static Latches and Registers I
--Video
-4.Static Latches and Registers II
--Video
-5.Static Latches and Registers III
--Video
-6.HW--作业
-6.PPT
--补充材料
-1.Key Points Review
--Video
-2.Dynamic Latches and Registers I
--Video
-3.Dynamic Latches and Registers II
--Video
-4.Dynamic Latches and Registers III
--Video
-5.Pulse Register
--Video
-6.Pipelining
--Video
-7.Schmitt Trigger
--Video
-8.Summary and Textbook Reference
--Video
-9.HW--作业
-9.PPT
--补充材料
-1. Introduction
--Video
-2. Adder: Full Adder (Definition)
--Video
-3. Adder: Circuit Design
--Video
-4. Adder: Logic Design I
--Video
-5. Adder: Logic Design II
--Video
-6. Adder: Summary
--Video
-7.HW--作业
-7.PPT
--补充材料
-1. Key Points Review
--Video
-2. Multiplier
--Video
-3. Shifter
--Video
-4. Summary and Textbook Reference
--Video
-5. HW--作业
-5. PPT
--补充材料
-1. Introduction
--Video
-2. Capacitance
--Video
-3. Resistance
--Video
-4. Electrical Wire Models
--Video
-5. Summary and Textbook Reference
--Video
-6. HW--作业
-6. PPT
--补充材料
-1. Introduction
--Video
-2. Capacitive Parasitics
--Video
-3. Capacitive Parasitics II
--Video
-4. Resistive Parasitics
--Video
-5. Summary and Textbook Reference
--Video
-6. HW--作业
-6. PPT
--补充材料
-1. Assignment Solving
--Video
-2. The teaching assistants want to say
--Video
-1. Problem 1
--Video
-2. Problem 2
--Video
-3. Problem 3
--Video
-4. Problem 4
--Video
-5. Problem 5
--Video
-6. Problem 6
--Video
-7. Problem 7
--Video
-1. Problem 8
--Video
-2. Problem 9
--Video
-3. Problem 10
--Video
-4. Problem 11
--Video
-5. Problem 12
--Video
-6. Problem 13
--Video
-7. Problem 14
--Video
