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Next we move to resistive parasitics

We have already learned how to drive RC interconnect

And impact of the resistance is commonly

seen in power supply distribution

For example the IR drop

IR drop means voltage drop.

I here stands for the current.

And R here stands for the resistance.

So IR drop stands for voltage drop

And also the voltage variations

And power supply is distributed to minimize

the IR drop and the change in current due to switching of the gates

IR introduced by noise.

I can give you an example.

So if the supply voltage here is VDD,

because we have the resistance here representing

the resistance of the wire.

Therefore the supply voltage of this inverter

is not equal to VDD anymore.

This one equals VDD minus ΔV‘. Ok?

And also if this is the ground.

Then we have resistance here.

Therefore the voltage here is not equal to 0 anymore.

It equals ΔV. OK?

if this is ΔV，

then the output of the inverter could only be pulled down to ΔV

So this is ΔV right?

So if this is ΔV. if it's very close to this node.

therefore this one equals ΔV,

which will turn on the transistor in some case. Right?

So this is the issue

This tells us the ohmic voltage drop

on the supply rails reduces the noise margins

And this foil makes it clear.

So you can see the resistance and the power redistribution problem

So you can see the,

here the gray-scale is used to indicate

the severeness of the voltage drop. OK?

So you can see here the voltage drop,

the IR drop here is very severe. OK?

Therefore it requires fast and accurate peak

current prediction and heavily

influenced by packaging technology

So we can use some techniques

to reduce the influence of IR drop

For example, from this one to this one,

you can find out the gray-scale here

is much smaller than that of this one

Which means the IR drop issue is reduced in some extent

And this foil tells us the power consumption,

the increasing power consumption

and increase of the current,

as this curve and this curve OK?

So we know the power consumption is increasing,

therefore need better cooling technology

And supply current is increasing faster

On-chip signal integrity will be a major issue

And power and current distribution are critical. Right?

So Approach to solve this problem

or slow down this problem is that

We can accelerate the supply voltage scaling

Or we can use material with low k dielectric

And thinner interconnect.

For example the copper

And SOI circuit innovations.

SOI means silicon on insulator

The transistors are constructed

in a very thin layer of the silicon,

deposited on top of the thick layer of the insulating,

for example SiO2.

And clock-system design and micro-architecture

This is the evolution of power-supply current

and supply voltage for different generations of

the high-performance,

Alfpha microprocessor family from Compaq

In terms of power distribution

So low-level distribution normally is meta1. Right?

Power has to be strapped in higher layers of the metal

The spacing is set by IR drop,

the voltage drop, electromigration and inductive effects

Always use multiple contacts on straps.

I will give you examples

So you can see if we have just one layout metal,

therefore we use this one as the GND and this one as,

serving as the power supply

And also maybe this one power supply,

power supply and these two serving as GND

This is just, this is power and ground distribution

This is called finger-shaped network

This is called network with multiple supply pins

And if we have three layers, three metal layers

The power supply from two sides of

the die via third metal layer, two sides

And second metal layer used to form power grid

90% of the third metal layer used

for power routing and clock routing

This is the third layer

If we have fourth layer like this

Power supplied from four sides, four sides of the die

And grid strapping done all in coarse metal

And 90% of the third and fourth metals used

for power routing and clock routing.

This is the fourth layer

If we have six layers. OK?

And this layer, this layer serves

as the VDD GND, VDD and GND. OK?

So you can solid planes dedicated to VDD

and GND significantly lowers resistance of grid,

lowers on-chip inductance

I will give you an example.

This one is designed by me, when I was a PHD student

So you can see, we have power stripe here,

and power ring, which is used to surround the core of the chip

The same is true

Here, you can find out we have the power stripe here, power stripe here

And the power ring here

Which is surrounding the core of the chip

In this foil, I like to introduce

the concept of the electromigration

A direct current in a metal wire running over substantial

time period will cause a transport of the metal ions.

For example if you,

the current running through the wire,

therefore the current will move,

will push the movement of the ions. Right?

So eventually this causes the wire

to break or to short-circuit to another wire

So the current density, in other words,

the current per unit area in a metal

wire is limited due to an effect called electromigration

So here you can find out the

line-open failure and also open failure in contact plug

All of these come from electromigration effect

The rate of the electromigration depends on the temperature,

the crystal structure,

and the average current density

So keep the current below 0.5

to 1mA/um normally prevents migration

At technology level, a number of precautions

can be taken to reduce the migration risk

For example, we can add alloying elements

such as Cu or Tu to aluminum

to prevent the movement of the Al ions

And to control the granularity of the ions.

And introduction of new interconnect materials.

Also in terms of the wiring I mean the routing,

and normally we use the Manhattan routing

Manhattan routing means from this point to another point,

we have to go horizontally and go vertically. OK?

So the Manhattan routing uses preferential

routing along the orthogonal axis,

for example from this source and destination,

we should go this way and this way. OK?

While diagonal routing,

which is different from the

manhattan routing allows for 45° lines

What does that mean?

So you can make routing this way,

this way directly from the source

to the destination directly rather than this way. OK?

Therefore this one have the advantage of 20%

or more interconnect length reduction

And also the clock speed,

signal integrity issue and power integrity issue

And also has 15% smaller chips in area,

it has area which is 15% or more small than previous one

Plus 30% more via reduction

This is the example we can see we use

the diagonal routing rather than

the manhattan routing in this picture. OK

So actually, we have different routing approaches.

And here I can give you another example

So in this picture, you can

find out we have many terminals

The dot here stands for terminal of the component. OK?

And also we have many obstacles

Here and our job is to connect the

terminals according to the applications

And we have to make sure we can avoid the obstacles, the blocks

And at the same time we can make sure the wiring,

the length of wire is minimized

How could we do that?

One approach is called current driven circuit model

This one, so this one

Compared with the already-existing best algorithm

such as this one, OARSMan and Forst,

All of these already-existing approaches CDCM,

the current driven circuit model can obtain optimal result when the

The terminal number is less than seven. OK?

Furthermore, with the increase of the terminal number,

the wire length obtained is on average 12% shorter

than those of the two algorithms,

while keeping about the same running time

So the basic idea is that the current will,

is much easier for the current

to flow through the pass with low resistance

It is the basic idea of this one

If you want to know this,

you can access the papers published by the inventor of this approach.

This is actually invented by one of my undergraduate student, the junior student

And he achieved, he is awarded the excellent

undergraduate dissertation of the Tsinghua University in 2002

So, I like to say that in terms of the wiring approach,

the routing approach, even the junior student can contribute to that. OK

And this one tells us,

we know the delay has a quadratic relation

with the length of the wire. Right?

Therefore, how could we reduce the delay of the wire? Previously,

I introduced that we can insert buffers like this. Right?

We insert buffers or repeaters, inverters.

Therefore the delay of this one equals,

tp equals m times this one

m is the number of the buffers. OK?

And R and C here stands for total resistance and capacitance

And r and c stands for resistance and capacitance per unit length

And the L stands for the total length of the wire.

And m stands for the number of the wire segments. OK?

And R equals r times L. and C equals c times L.OK?

Therefore this is the delay of the segment. Right?

And we can partial derivative tp over m, and let it equals 0.

Therefore the value of the m could be optimized,

could be derived, equals this one. OK?

L times square root of 0.38 time rc over tp,buf. OK?

Therefore the tp optimized equal this one

tp,wire,buffer equals 0.38 times r times c times L square.

However this is our, I have to say that this is too optimistic

Actually, I introduced this before. Right?

Too optimistic. Why is that?

So you can see, actually we have to consider

When we calculate the delay of the segment,

we have to consider the influence of all the capacitance,

including the capacitance of this buffer. OK

so if we replace this one,

if we replace this one by this model. OK?

By this model. So this is

The R and C are still the total resistance and capacitance

Rd and Cd stands for the output resistance.

This is output resistance and Cd is the

gate capacitance of minimum-sized repeater. OK?

And s stands for sizing factor or scaling factor of the repeater.

And γ stands for proportionality factor,

the ratio of the output capacitance of the repeater

to the input capacitance of the repeater. OK?

If we use this one to model this segment, what will happen?

So we know that the time constant equals this one

So this is the resistance of this one times the capacitance of this one

This is resistance of this one plus

the resistance of the wire times the capacitance of this one

Here please don't forget one over two

Because this is distributed rc model.

And this one stands for the resistance of

this one plus this one and multiplied by the capacitance of this one.

Therefore after the manipulation,

you can see this is lumped model

and this is the distributed model. OK?

In terms of the real delay. This one,

the lumped model should be multiplied by 0.69

and distributed model should be multiplied by 0.38.right?

So this is the delay of the one section

This is lumped. This is distributed

So if this is the delay of one section,

then we can calculate the delay of all the sections.

We can sum them, sum them up. Right?

Therefore the tp equals this one. OK?

According to the expression of the tp,

we can make partial derivative of tp over the m.

and also partial derivative tp over the sizing factor. OK?

And equate them to zero.

Therefore the m is derived as this one. OK?

Here, we define this one as the delay of

an inverter for a fan-out of one. Right?

The fan-out equals one, this is the delay of that one, OK, defined as tp1

In this case the sizing factor equals this one

And tp,min, the minimum time of the tp equals this one. OK?

So here you can find out the delay has a linear relation with wire length

Rather than the quadratic relation with the wire length

For a given technology and a given interconnect layer,

there exists an optimal length of

the wire segments between repeaters

So we know the optimal value of m.

Therefore we can calculate the Lcrit. Right?

This one, Lcrit equals this one.

So in other words, it doesn't make any sense

to introduce repeaters as L is less than 2Lcrit

Also the delay of a segment of critical

length is independent of the routing layer.

We can see tp equals this one.

So this one doesn't have any relation with the routing layer

And in the last foil,

we like to see that wire is a big issue. Right?

So wires have to be considered

early in the design process,

and can no longer be treated as an afterthought

as was most often the case in the past

For example. This is the wire.

So we can in the extreme case,

we should insert registers to pipeline

the transmission of the signal in the wires. Right?

This is just don't have any logics here,

but we can still insert the registers

to pipeline the transmit of the signal

So we should consider the influence of wire in advance. OK?

Things are totally different from our previous approaches