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At first the capacitive parasitics.

Here, in this foil

I would like to give an example

so you can we have a voltage source here

and this is a line named as X,

and another line which is the floating line named

as Y such as the floating node of dynamic circuit. OK?

So we know that capacitance between the Y,

line Y and the ground equals CY

and coupling capacitance

or parasitic capacitance between X and Y is named as CXY.

And delta VX stands for the voltage step change on the node X,

and delta VY stands for the voltage disturbance on the node Y.

Therefore node Y could be expressed as CXY over CY plus CXY times delta VX.

This is because of charge conservation.

So the circuits susceptive to crosstalk

is that the dynamic network circuits,

you still remember in the dynamic circuit

we have two phases the first one is pre-charge phase,

the second one is evaluation phase so after the precharge phase,

if the pull down network is not conducting,

I mean in terms of N logic, OK?

Therefore the output is floating, right?

So it is very sensitive to noise,

so dynamic network circuit especially

the networks with low swing precharged nodes,

located in adjacency to full swing wires.

So here we have a definition of crosstalk which means

an unwanted coupling from a neighboring signal

wire to a network node introduces an interference

that is generally called crosstalk.

This is an example for the previous foil,

we can see if this is a dynamic circuit and if the aggressor here

this is X this is aggressor, and Y is victim,

if the aggressor makes transition

for 0 volt to 2.5 volt, what will happen on the Y?

If we assume that CY equals 6fF

and CXY as a coupling capacitance between node Y and X, right,

and line X is implemented by AL1,

and line Y is implemented by polysilicon.

And we assume that overlap area between AL1

and polysilicon is 3 times 1 um2.

Also we suppose that node Y is precharged to 2.5V

and signal X undergoes a transition from

this one to this one, 2.5 volt to 0 volt.

So calculate the voltage drop delta VY

caused by charge redistribution on node Y.

So, according to the, you still remember

how to calculate the overlap capacitance,

we should take into account the parallel plate capacitance

as well as the fringing capacitance

so this one is the parallel plate capacitance,

and this one is the fringing capacitance.

So two sides of the wire should be taken into account.

And we can find out the CXY equals 0.5fF,

and therefore delta Y could be calculated by this expression, right,

which is equal to -0.19 volt.

So therefore you can find out a keeper,

a keeper here needed in dynamic circuit to come to the driven situation.

So you still remember this one.

the 57fF micro square comes from this number, right,

in our previous lecture and 54 for

the fringing capacitance comes from this number.

How about the reliability and crosstalk issue,

I can give you some conclusions,

the first one is that you can see we have a voltage source here

and we have a line X here,

ok this is the aggressor, and this is victim.

And line Y is connected to the voltage source,

or current source through a resistor.

And Ry the resistance of the driver

and this is the capacitance CY between this node and ground,

and this is the coupling capacitance between X and Y.

Then the time constant of this circuit

equals τxy equals RY times CXY plus CY,

and this figure tells us the response

for different rise times of VX,

if the VX, the rise time of the VX equals,

the tr equals 5 ps you can find out very huge,

very huge disturbance, right,

if the rise time of the VX equals 100ps,

then that is smaller than that of this one,

when this one equals the tr equals 500ps

and this one is the smallest one, I mean among the others.

So in other words if the rise and fall time

of the aggressor of the input is small

then we can find out disturbance is very high,

otherwise if it is very long,

then the disturbance relatively low.

So conclusion one is that it's better

for us to keep time constant

this one smaller than the rise time or fall time,

that is very important.

In this case you can find out

the RY equals this one 10KΩ,

and CY equals 20fF, and CXY equals 5fF.

Then time constant equals this one plus this one,

multiplied by this one. That is 250 ps.

So it's better for the tr bigger than this one,

otherwise the disturbance is relatively very high.

And the second conclusion is that you can find out

in this picture that if the aggressor,

for example this is an aggressor,

if the victim is undriven,you can see the amplitude of

the disturbance relatively very high.

And if the victim, I mean this one,

victim is half size driver,

I mean has half size driver

Then the amplitude just 16 percent,

and this one equal size driver is 8 percent,

if double size driver, that is 4 percent.

Which means the nodes with high resistances

are susceptive to crosstalk.

So that's why we want the node is either

connected to power supply or ground so

we have the same meaning, right,

so it's better to keep this one as much as possible

to avoid the disturbance from the aggressor.

How could we deal with reliability

and crosstalk issue?

The first approach is that we should avoid

floating nodes if all possible,

for example we can use the keeper decrease

the resistance for example this one,

we use the keeper to make sure that

this node is static rather than dynamic, right,

and also still remember the DG gate,

this is Goliath, this is G, this is David.

So we use a small inverter to make

this node pseudo static, right,

so the first approach is to avoid floating node if all possible.

The second approach is that the sensitive

nodes should be well separated from full swing signals.

So if we have a static node, static aggressor,

for example, if we have another dynamic circuit

so it's better for us to well separate

the dynamic circuit from the a static circuit.

The third one is that to make the rise

and fall time as large as possible,

subject to timing constrains.

Direct path power consumption will therefore increase. Right?

Because if the rise and fall

time is very very large, OK?

Therefore, during transition of,

for example the inverter,

therefore we have a current directly

from power supply to ground,

so that's an issue, right,

but if the rise and fall time

is large therefore the crosstalk

issue will turn to be very low.

The forth approach is that use differential

signaling in sensitive low swing wiring networks,

so this turns the crosstalk signal into a common

mode noise source that does

not impact the operation of the circuit.

The fifth approach is do not

run wires together for a long distance,

for example if this is the wire and another wire,

it's better not to run these

two wires for long distance, right,

and also make parallel wires

on the same layer away from each other.

So it's better to move this one

and this one away from each other, as far as possible. Right?

And the sixth approach,

we can provide a shielding wire for example the ground

and power supply between the two signals.

This effectively turns the interwire capacitance

into a capacitance to ground and eliminates interference.

I give you an example,

so you can see here,

we have some signals,

a0 a1 a2 and a3,

we insert the VDD here and ground here and VDD here, right,

so this is called shielding wire.

Put shielding wires GND and VDD

at one side of the sensitive wire.

The second one is that we can put shielding

wires more conservatively for example,

the GND and VDD at two sides of sensitive wire.

So this one, this is a signal and we put VDD here,

next to the a0, and also the GND here,

next to a0. OK.

This is a very very conservative approach.

The third one is that we can interpose

one set of wire into the other set of wire,

for example this is a0, a1 a2,

this is one set of wire and another

set of wire is b0 b1 and b2,

so we can interpose a bus and b bus, if we can make sure,

if and only if we can make sure,

that a bus and b bus would not toggle at same time.

The seventh approach is that the interwire

capacitance between signals on different layers

can be further reduced by the

addition of extra routing layers.

For example this one,

so we can add an extra routing layer

which is specifically for the implementation

of the ground or the VDD,

this is called shielding layer

which is used to isolate this layer and this layer.

So this is called cross section of routing layers.

And the eighth problem is that

we can use repeater or buffer to make

the wire less sensitive to noise.

What does this mean?

Let me give you an example.

If here, we have a driver,

and we have a receiver here,

and they are connected through a wire along very long wire.

And in this case we can insert buffers or inverters

to divide the wire into different, several segments.

Therefore the resistance and capacitance

of the wire are reduced, right,

because this one, resistance of this one,capacitance of this one,

is smaller than that of whole wire.

The ninth approach is that

we can adopt staggered repeaters,

for example, if this is an aggressor,

this is a victim, and in the aggressor,

we can add the inverter here for example,

and we know they have coupling capacitance

between the victim and aggressor,

for example after we add the inverter here

then if the input makes transition from 1 to 0

and here this is also a victim we have the voltage drop. Right?

However at the same time because we have an inverter here,

therefore the output of the inverter, this transition from 0 to 1.

The same will happen here,

this one will have a voltage increase, right?

Therefore the coupled noise cancels each other.

And the tenth approach exploit charge compensation technique,

for example this is an aggressor,

this is victim,

and we can add inverter followed by

this one here, this one is to connect

the source of the transistor, the drain of the transistor.

So if the source is connected to the drain,

then this transistor servers as a capacitor, right,

so actually this circuit is something

very very similar to this circuit, right,

so we can find out that coupled noise cancels

when signal passing through this kind of circuit.

And this approach

is called you can twist the differential signals,

for example,

if you want to transfer signal a,

at same time we transfer signal a bar, OK,

a and a bar v and v bar, OK?

so this is aggressor, aggressor bar,

this is victim, this is victim bar,

therefore you can see right here,

so a, when the a makes transition,

this one from this direction

then a bar makes the opposite direction transition. Right?

So the coupled noise cancels,

the same is true that here the coupled noise cancels.

That's why we can twist,

why we twist differential signals.

And the delay we know that

depends on activity in neighboring wires,

for example we have 3 transmitter here,

we have 6 receiver here,

and the capacitance between X and Y equals Cc,

the Y and Z equal Cc, OK?

So when neighboring lines switch in opposite

direction for example when this one makes transition from 0 to 1,

this one from 1 to 0, this one from 0 to 1,

therefore the total capacitance

on node Y will reach C ground plus 4 times Cc, right,

because this one has opposite direction of this one,

and this one has the opposite of this one.

And when neighboring lines switch in

the same direction of victim line,

when they switch in the same direction,

then the total load capacitance is equal to C ground,

therefore you can see,

the range of load capacitance of CL is from C ground

to C ground plus 4 times Cc,

and C ground here stands

for capacitance between node Y and ground.

And this foil makes it increasingly clear,

you can see the delay equals g times Cw times this one,

this one stands for the resistance of the wire,

this one stands for the resistance of the driver, OK?

Because this one should follow the distributed rc

model therefore the coefficient equals 0.38,

coefficient of this one which

should satisfy the lumped model, equals 0.69,

and here Cw stands for the capacitance of the wire.

And the g here stands for the delay factor,

you can see in this picture that the delay

ratio factor g for bus wire as a function

of simultaneous transitions on neighboring lines.

So you can see in this case,

in this case the bit K-1 and bit K and bit K+1,

all of these signals make same direction transitions.

Therefore the capacitance between

this one and this one is 0,

ok therefore g equals 0,

and here because this one has same direction of this one,

however this one has opposite direction of this one,

therefore the g equals 2 times r,

2 times r here stands for the ratio

between capacitance to neighbor and to ground. OK?

This is 2 times Cc, in this case

this one has opposite direction of this one,

bit K and bit K has opposite direction of bit K + 1,

therefore the capacitance between this one K-1

and K equals 2 times Cc and between K and K+1,

equals 2 times Cc, therefore the delay factor equals 4 times r.

So the typical techniques to predict the delay of the wire,

we can actually have 3 kind of techniques,

the first one we can evaluate and improve,

what does this mean?

It means we can extract the parameters

then we can do simulation then we can modify

then we can do parameter extraction again,

one more time.

This is actually the most often used approach,

however many iterations needed

and it is very very time consuming. Right?

The first approach.

The second approach is that we can use

constructive layout generation approach,

wire routing programs that one can take into account

the effects of the adjacent wires, which means we can,

it is very very talent, right,

we can consider the influence of different effects in advance,

it is very very appealing right?

However very complex,

too complex to be realized currently.

The third approach is that predictable structures

we can use a regular and predictable wiring topologies,

it may be the way to address the capacitive crosstalk problem.

It actually is the only approach that

is really workable in the short haul.

A very conservative approach but very very useful and workable.

Let me show you.

So we can use structured predictable structure here,

such as this one, this is a signal,

S stands for signal,

and we the insert voltage here,and the ground, the voltage,

supply voltage VDD, the ground and VDD,

they are in parallel.

And another layer is in, they could not be in parallel,

this one should be in perpendicular with this one. Right?

And also the VDD and signal and ground

and signal and VDD and signal. Right?

S, V and G stand for signal, VDD and GND.

And this is trade-off,

the cross coupling capacitance is decreased by 40 times lower

and we have 2 percent delay variation,

and also increase in area and overall capacitance,

is very very frequently used in FPGA and VPGA.

FPGA here stands for Field-Programmable Gate Array,

and VPGA stands for Via-Programmable Gate Arrays.

And in terms of the dielectrics,

we prefer the low-k dielectrics,

for example here,

the both delay and power are reduced

by dropping interconnect capacitance.

And types of low-k materials included by

dropping interconnect capacitance,

for example you can see in different generations

for example this one, 0.25um, and 0.18um to 0.05um,

and we have different dynamic constants,

we can see the decrease of the dielectric constant.

And also we can encode the data to

avoid worst case conditions for example if we,

this is the input and output,

if we can encode the input to avoid

the neighboring transitions

in the signals of the bus,

and also remains data dependent.