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So how to drive large capacitances,

we have many different large capacitances

in the circuit for example the clock signal,

so we know that we have one clock input,

then clock will drive all the registers

and all the latches in the counters the memories, right?

so clock signal has a very large capacitance,

and also bus signal, because this is the bus

so many components are connected to bus,

and also some control signals,

such as the reset because every register

or every latches has a reset, reset or set signal.

And data and control bus in memory,

and used to connect hundreds of transistors.

And also the drivers on off-chip load normally around several pF.

For example the PAD.

So how could we drive the large capacitances?

Actually we have learned that before, right,

you still remember that the inverter

chain and if we want this one,

I mean the first inverter to drive large capacitance

we should design an inverter chain,

at that time if we know the CL so how to choose

the number of stages so as to minimize the delay?

And how to determine the sizing of the inverters

Let's go to revisit our previous conclusions,

the first one is that if we know the number of stages therefore the f,

the sizing factor equals the N root of F,

the F equals CL over the input capacitance of first inverter, right?

therefore tp equals N times tp0,

tp0 stands for intrinsic delay,

times 1 plus N root of F over r.

This is the condition that we know the number of stages.

If the number of stages is not known,

therefore the f is normally chosen to be 4 or 3.6, right?

and the N equals the lnF over lnf, OK?

And tp equals this one,

and here theγis determined by technology

and normally set to be 1 for most micro processes,

I've already introduced this before. Right?

So according to this,

for example I give you the CL equals 20pF

and the input capacitance of the first inverter equals one,

therefore we can calculate,

if we know this one,

if we know the input capacitance of the first inverter,

therefore we can calculate the,

if we can find out for the CL over this one equals 8000, OK,

then according to the previous approaches

we can obtain that if f equals 3.6

and number of stages equals 7,

therefore tp equals 0.97ns. Right?

So in this table we can list the size of

each transistor in this inverter chain,

so for example this is the size of first inverter,

the size of PMOS transistor, size of NMOS transistor,

this is the size of second inverter,

size of the third inverter,

forth inverter, to the size of the seventh inverter.

And we have seven stages,

and f equals this one, 3.6, and βequals 1.9,

and tp equals 0.97ns.

In this case you can find out yes it makes sense

that we minimize of this propagation delay,

however you can find out one important issue here, what is that?

You can see we have a very huge transistors,

for example this one,

we have 1500 micron which is like this, right,

and this one is 800 microns,

this is the width of the NMOS transistor,

so it's not easy actually it is impossible

for us to implement such huge transistors, OK?

We know this is a minimum sized,

the width of the minimum sized reference inverter,

which is 0.375,

so this is much huge than this one,

so that's an issue. Right?

So this solution obviously requires some extremely

large transistors with gate width of up to 1.5mm,

which equals several thousand minimum sized inverters.

So how could we deal with this in the real case?

So we should make some assumptions,

so if we can assume that if we know the performance,

the constrains of the performance,

therefore we can trade off between the performance,

I don't have to always minimize performance, right?

so we can trade off between the performance

for area and energy reduction. What does this mean?

If we give a maximum propagation delay time tp,max,

you can determine the number of buffer stages N

and required scalling factor f,

such that the overall area is minimized.

This is equivalent to finding a solution

that sets tp as close as possible to tp,max.

So you can see if we know tp,max,

tp,max should be greater than tp0 times lnF time

1 plus f over γ then over lnf, ok,

this one equals this one, OK,

this is our first expression.

The second one we can find out the relation

between overall area and the sizing factor f,

so this area,

this is 1 plus f plus f square then to power

of N-1 times the area of the first inverter,

then after the manipulation,

this one equals f power of N minus 1 over f-1 times

area of the first inverter,

so this one equals this one. Right?

So from these two we can find out the smaller N,

if we have smaller N, f is therefore bigger,

the smaller area consumption we have, right, from this expression.

And how about the energy consumption?

The overhead energy could be expressed as this one,

so Edriver equals this one stands for the overall

capacitances times VDD square, and capacitance equals,

the input capacitance and intrinsic capacitance,

for example, takes the first inverter for example,

this one equals 1 plus γ times Ci,

the second one equals f times 1 plus γ times Ci,

and to the end we have f N-1 times 1 plus γ times Ci, ok?

So after manipulations,

we have we can see that Edriver approximately

equals 2 times CL over f-1 times VDD square.

This is under the assumption that

the F-1 times Ci approximately equals CL,

and also γ approximately equals 1. OK?

So from this expression we can find out

the smaller the number of stages the smaller N,

the smaller energy consumption. Right?

So if we know that the F equals CL over Ci equals 8000,

and tp,max is set to be 2ns, and tp0 equals 30ps,

therefore tp,max over tp0 equals 667. Right?

Therefore from this picture we can find out this is tp over tp0,

the tp,max over tp0，

as a function of number of the stages.

You can find out if we set number of stages to be three,

therefore the tp over tp0 euqals this one,

could be satisfied, could be satisfied, right?

So, if we only have three stages,

the width of each transistor could be minimized,

could be reduced substantially, right?

For example, the first one, the size of first one,

the size of second one, the size of the third one, right?

However, the area,

the propagation delay of this one is bigger

than the previous one, almost two times, right?

So,the overall area of the new design

is approximately 7.5 times smaller than the optimum solution,

while its speed is reduced by less than a factor of 2. OK?

So,you can see, we substantially decrease

the width of transistors and area of transistors

at the cost of reduction of the performance, right?

But, the performance,

we don’t have to minimize performance

and our objective is to make sure the performance,

satisfy our constraint, right?

So, if we can make sure the performance satisfy our constraint,

therefore we can reduce the area of each transistor, right?

However, still we can see,

here the width of transistor is still very high. Right?

This one we have, even though,

this is much smaller than this one,

however we still have 284 and 150 micro which is like this.

So how could we implement this in real situation?

So, you can see this is the layout

of final bounding-pad driver.

So, we, the drain of the transistor,

this is the source of the transistor, this is the gate.

So we actually design the architecture

called finger-shaped architecture to implement the high,

I mean, the strong transistors,

the transistor with big width, OK?

We actually implement the transistors. OK.

So let them in parallel.

So this one in parallel with this one,

in parallel with this one.

Therefore, this one can provide the same

driven capability of the transistor with the very wide width. OK?

So this is called finger-shaped architecture,

just like this one. So you can have a finger,

and another finger, ok,

finger-shaped architecture.

So this is the layout of the die,

you can see we have pad here, around,

this is a die, right? And we have pads around the die.

This is the microphotograph of

the die in the die taken by the microscope.

And here, you can find out this is a die,

and this is a pad, we use the bonding wire to bond

the pad to the lead frame. OK?

And here, if this is a die, and this is a pad,

this is bonding wire, and if we have a lead frame,

and we have a bonding wire here.

So, that’s why we can connect the core of,

the logic in the core, to the outside world,

and also we know that the pad should

drive very huge capacitance, normally.

So we design the pad. For example,

this is an output pad.

We normally use this kind of architecture,

the finger-shaped architecture,and this is a pad,

this is a finger-shaped one to implement

the approach to drive the high,

very high, very huge capacitances.

And this foil tells us how to design tristate buffers,

we can see we have circuit like this,

this is connected to the enable bar,

this is connected to enable.

So when the enable equals 1,

when this is one, this is,

therefore this is on, this is on,

therefore the In is copied to Out, right?

When the En equals 0, then this is off,

this is off, then output is floating.

The same is true that the,

so this is called tri-state,

1, 0, and the high impedance states.

The same is true that we have this kind of architecture,

so Out equals In and En plus In and En bar.

So in this kind of technology we can implement tri-state buffers.

So two possible implementations of this one

and this one and En equals 1 enables the buffer.